Stratix GX devices are a powerful fusion of 3.125-Gbps transceiver technology with the industry's fastest FPGA architecture. Drawing on valuable experience gained as the first FPGA company to embed high-speed transceivers in FPGAs, Altera designed Stratix GX devices to minimize design implementation risks. This is made possible by providing customers with not only silicon that functions to specifications, but also with the critical software, intellectual property, characterization information, documentation, and board design tools necessary for simplifying complex, multi-gigabit designs.

Multi-gigabit system design requires more than just a functional FPGA. Altera delivers a complete design platform that includes silicon, software, intellectual property (IP), a comprehensive support infrastructure, documentation, board design guidelines, product interoperability testing, and development kits and boards. This comprehensive platform ensures that designers have all the tools they need to create a working transceiver-based system, be it for backplane or chip-to-chip applications. Using these tools, designers eliminate potential issues that could arise during the design process and minimize implementation risks.

Stratix GX devices feature multiple gigabit transceiver blocks, each with four full duplex channels. Using clock data recovery (CDR) technology, these channels serialize or deserialize data for transmission rates up to 3.125 Gbps. Each channel features dedicated circuitry that implements various stages of the data recovery and transmission, decoding and encoding, and manipulation processes. A seamless interface with the programmable logic ensures reliable data transfer, maximized data throughput, and simplified timing analysis.

Gigabit transceiver block highlights include:

• Support for transceiver protocols including the 10 Gigabit Ethernet XAUI, SONET/SDH, Gigabit Ethernet, Fibre Channel, InfiniBand, Serial RapidIO™, PCI Express, SMPTE 292M, SFI-5, and SPI-5 protocols
• Low power consumption per channel (175 mW) and per gigabit transceiver block (450 mW)
• Programmable pre-emphasis, equalization, and differential output voltage settings

Source-synchronous I/O channels capable of 1-Gbps performance balance data transfer through the device. These channels, located on the opposite side of the device from the transceiver blocks, enable users to move data on and off the device using the LVDS, HyperTransport™, or LVPECL I/O standards across multiple channels. Each channel is equipped with embedded SERDES technology to simplify design implementation.
Recognizing the challenges that engineers face when designing systems that transfer high-speed data without CDR technology, Altera incorporated the dynamic phase alignment (DPA) feature into Stratix GX devices. This feature dramatically simplifies printed circuit board (PCB) design, eliminating signal alignment issues introduced by skew-inducing effects when using source-synchronous signaling techniques. DPA eliminates timing issues that potentially could lead to initial product deployment delays. Using DPA, designers can focus on system implementation and optimization rather than complex board design issues.

Stratix GX devices are based on the new, high-performance Stratix device architecture and offer the same revolutionary features:

• Abundant TriMatrix memory for on-chip storage
• Robust clock management and frequency synthesis using embedded phase-locked loops (PLLs) for managing on- and off-chip timing
• Fast external memory access with dedicated interface circuitry to DRAM and SRAM devices
• Maximized signal quality and data transfer reliability with Terminator™ technology for differential and single-ended I/O standards
• High-bandwidth DSP blocks for signal processing-intensive applications
• Remote system upgrade feature that ensures the reliable and safe deployment of system upgrades and bug fixes