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| Altera
Introduces the Future of Programmable Logic - Stratix
Device Family |
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Altera begins a new age in digital
design with the Stratix¢â device family, powering complex
designs to new levels of system integration. In concert
with the LogicLock¢â design methodology, Stratix devices
simplify the difficult process of design integration,
providing the basis upon which block-based designs
can be developed and optimized for maximum performance.
Stratix devices offer an average performance increase
of 40% over previous architectural generations.
The rapid deployment of next-generation systems has
been accompanied by a dramatic increase in demand
for total programmable logic device (PLD) bandwidth,
including core processing, memory, arithmetic, and
I/O bandwidth. Stratix devices are specifically designed
to meet the needs of bandwidth-hungry designs, incorporating
significant advances in memory design, processing
power, and I/O flexibility. Rather than being restricted
to non-critical peripheral processes, Stratix devices
can be used at the heart of these high-bandwidth systems
to accelerate performance and enable new functionality.
The Stratix device family is based on a 1.5-V, 0.13-¥ìm,
all-layer-copper process technology and offers up
to 114,140 logic elements (LEs), 10 Mbits of embedded
memory, optimized digital signal processing (DSP)
blocks, and high-performance I/O capabilities. Stratix
devices are the ideal solution for complex, high-performance
systems.
Stratix devices have a rich set of advanced features,
including:
- A high-performance architecture that accelerates
block-based designs for maximum
system performance
- Abundant TriMatrixO memory resources for on-chip
storage
- High-bandwidth DSP blocks for signal processing-intensive
applications
- Proven differential I/O technology featuring the
True-LVDS¢â circuitry, capable of
840-Mbps performance
- Robust clock management and frequency synthesis
for managing on- and off-chip
timing to maximize system performance
using full-featured, embedded phase-locked
loops (PLLs)
- Maximized signal quality and data transfer reliability
with TerminatorO technology for
differential and single-ended I/O standards
- Configuration error recovery circuitry for reliable
and safe deployment of remote system
upgrades and bug fixes
When used in conjunction with an extensive intellectual
property (IP) core portfolio and the easy-to-use Quartus¢ç
II development software version 2.0, users can rapidly
implement their high-bandwidth designs while minimizing
time-to-market. |
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Logic
Design
