1.
What are the business guidelines for design migration
from PLDs to HardCopy devices?
The business guidelines are as follows:
Availability of a fully functional Altera PLD
design file. The PLD design should be stable and
frozen, and the PLD device must be working in
the customer's target system.
Compliance with the expected design rules for
smooth design migration. Any non-compliance will
delay execution.
Design migration is strictly one-to-one. No
additional features or design changes are acceptable.
Identical performance in the HardCopy device
and the PLD. The performance of the HardCopy device
must be verified based on the original PLD performance.
Minimum order quantity and non-recurring engineering
(NRE) requirements. The customer must meet the
minimum order quantity and NRE requirements.
2.
Can additional prototype devices be ordered? If so,
what is the unit cost and when must Altera be notified
of the request?
Additional prototypes may be ordered
at 1.5x of the production unit price. You must place
the order for additional prototypes when paying the
NRE charge.
3.
Can HardCopy devices be purchased from Altera's authorized
distributors?
Yes, HardCopy devices may be purchased
from our authorized distributors.
4.
Do customers pay royalties for ARM-based Excalibur
embedded processor HardCopy devices?
No, at present customers will not
be required to deal with IP vendors or pay any kind
of license or royalty to ARM.
5.
What is the license and/or royalty scheme for the
MegaCore® and AMPPSM IP functions?
According to the current business
model, customers migrating from PLDs to HardCopy devices
will not pay any extra licensing fee for Altera MegaCore
functions that they use. We are working with the IP
partners to produce a business model for the AMPP
megafunctions.
6.
What are the deliverables for design migration from
a PLD to a HardCopy device?
The deliverables are as follows:
Quartus II software-generated .sof file
Quartus II software-generated .csf.rpt file
Quartus II software-generated .pin file
Quartus II software-generated .sdo file formatted
for use with Cadence VerilogXL
Quartus II software-generated .vo netlist formatted
for use with Cadence VerilogXL
Timing requirements file created in the template
supplied by Altera
Completed design information form
Completed questionnaire
Signed copy of HardCopy agreement
Non-cancelable purchase orders for the minimum
yearly quantity and NRE charge
Welcome to MJL Technology Ltd.
Copyright (c) 2007 MJL Technology. All
rights Reserved. Send e-mail to
MJL
Logic
Design
