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| Technical Question &
Answer |
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Technical |
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| 1.
Can Altera guarantee that the timing of a HardCopy
device is the same as that of a PLD? |
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Yes and no. HardCopy timing parameters are typically
faster than the worst-case PLD parameters. The migration
does not aim to conserve identical timing to the
PLD. Altera will take all the timing constraints
of the design into consideration and ensure that
no violations occur. This means that the individual
HardCopy timing path will be equal to or faster
than the corresponding timing path on the PLD. As
all timing paths do not necessarily speed up by
the same percentage, asynchronous circuitry should
be avoided.
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| 2.
Can Altera provide extraction timing data after HardCopy
placement and routing? |
| Extracted timing will be generated
after place & route. The extraction accuracy is
between 2.5-D and 3-D. Altera will use this extracted
timing data for verification. Currently, Altera does
not plan to provide timing data to customers. |
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| 3.
Sometimes it is very difficult to have a fully synchronous
design. There can be some asynchronous paths, such
as in a multi-clock domain design, where a path goes
from one clock to another. Can you still guarantee
timing in this situation? |
| To guarantee the timing, we require
the customer to describe all the timing constraints
in the design. This includes all clock domains, false
paths, timing exceptions, input and output delays,
and so on. |
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| 4.
What happens if design rules are not followed? |
| The design guidelines exist to ensure
the highest possible degree of success for the HardCopy
implementation of your design. If the designer does
not adhere to the design guidelines, the HardCopy
migration may take longer than expected. |
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5.
What happens if the customer's system tries to configure
the HardCopy device?
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| The HardCopy device has a built-in
state machine that recognizes external download activity
and will respond with an appropriate "DONE"
signal after the expected amount of time. |
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6.
Will minimum timing in HardCopy devices be supported
(required for I/O issues with tSU and tCO)?
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| Minimum timing will be generated for
HardCopy devices, in addition to maximum and typical
timing information. All delay corners will be checked
against the PLD timing with a static timing analysis
tool. |
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7.
What is the ICCSTANDBY current in a HardCopy device?
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| The ICCSTANDBY current is expected
to be the same as the Altera high-density devices.
This is because the circuits that consume static current
in the PLD (e.g., power-on-reset, phase-locked loop
(PLL), and LVDS I/O buffer) will operate in exactly
the same mode in the HardCopy device. For reference,
the specification for an APEX 20KE device -1 speed
grade is 10 mA. |
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8.
Will there be any difference in the I/O timing between
the PLD and the HardCopy device?
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| Yes, the timing between the two devices
will be different. The HardCopy I/Os will be marginally
faster than the corresponding PLD. |
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9.
Will Altera be able to guarantee minimum timing?
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| Minimum timing will be automatically
generated for the HardCopy design because it is needed
for hold-time checking. We will also use it to check
for any minimum tCO times required. |
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10.
Can the SignalTap logic analysis be left instantiated
so that a design does not have to be recompiled?
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| Yes, it is possible to do this. However,
you will not be able to use the SignalTap logic analyzer
in the HardCopy implementation because it will give
unexpected results. |
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11.
Does the HardCopy device contain the same test circuits
as the PLD?
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| No, the HardCopy device is tested
in a fundamentally different way than the PLD, so
the test circuits are different. |
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12.
How does the HardCopy clock skew compare to that
of the Altera high-density devices?
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| The expected clock skew on HardCopy
devices will be less, because the clock tree covers
a physically smaller area and the clock loading is
much less. |
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13.
Are there any additional I/Os in HardCopy devices
for testing?
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| No, all test pins are multiplexed
with regular I/Os. The test mode is selected in the
same way as for the PLD. |
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14.
How do you maintain the pin placement to the original
PLD?
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| The package pin-out is identical to
the PLD, but the bump placement on the HardCopy die
is physically different than on the PLD. Care has
been taken to match the placement of critical signals,
such as LVDS I/O. |
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15.
For a boundary scan, what happens to all the unused
I/O pins in a HardCopy device?
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| The unused I/Os are still in the HardCopy
base and are always connected into the JTAG chain,
just like the unused I/Os in the PLD. However, there
is one important difference between a PLD and a HardCopy
device: the boundary scan order is not the same. Therefore,
it is necessary to use a boundary-scan description
level (BSDL) file that has been created for a specific
HardCopy device, but a single BSDL file will be valid
for any design implemented on a specific HardCopy
base. For example, one BSDL file can be used for any
HC20K1500 design and another BSDL file for any HC20K1000
design. |
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16.
Will the customer have to generate board-level test
vectors due to the changes in the HardCopy boundary-scan
chain ordering?
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| Yes, the customer must generate the
board-level test program for migrating from an high-density
device to a HardCopy device. The board-level test
program has to be regenerated because of the differing
boundary-scan chain ordering. |
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Logic
Design
