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Logic Design

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▶ HC Stratix

▶ HardCopyII

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Home > Product & Solution > Logic Design > Device Families > HardCopy

Technical Question & Answer

General (click)

1.	What are HardCopy devices?
2.	Which devices will be available for migration into HardCopy devices?
3.	What kind of cost reduction can HardCopy devices provide?
4.	What is the migration risk? Are functionality and timing guaranteed?
5.	Is it possible to combine multiple PLDs into one HardCopy device?

Products Supported (click)

1.	Will the HardCopy devices support smaller APEX 20KE devices?
2.	Will the HardCopy devices support FLEX 10K® devices or other mature Altera PLDs?
3.	Will the HardCopy devices support the all-layer-copper APEX 20KC devices?
4.	Will the HardCopy devices support Excalibur products? Will HardCopy devices support the Nios™ soft embedded processors?
5.	What is the lead-time for prototypes and production units?

Design Methodology & Flow (click)

1.	What tools do customers need to migrate a PLD to a HardCopy design?
2.	Will Altera provide a gate-level HardCopy netlist to the customer for functional verification?
3.	Are any utilities available for customers to check the design before submitting it for HardCopy migration?
4.	Will the Verilog netlist file and .sdf file be released to the customer for verification?

Features (click)

1.	How much die size reduction is achieved by migrating a design to a HardCopy device?
2.	How much die size reduction can be expected for an ARM®-based Excalibur HardCopy device?
3.	What kind of performance improvement will be achieved by migrating to a HardCopy device?
4.	Can intellectual property (IP) cores be migrated to HardCopy devices?
5.	Do HardCopy devices support Joint Test Action Group (JTAG), LVDS, and other features available in Altera high-density devices?
6.	Will HardCopy devices consume less power than PLDs? If so, what will be the power consumption rate?
7.	Will HardCopy devices be available in the industrial temperature range?
8.	Will I/O performance be the same in HardCopy devices as in the original PLD?
9.	Are the same PLLs supported in HardCopy devices?
10.	Are ROM and RAM supported in HardCopy devices?
11.	If pre-load RAM is not supported, how can ROM be implemented?
12.	Are content-addressable memory (CAM) and product-term logic supported in HardCopy devices?

Technical (click)

1.	Can Altera guarantee that the timing of a HardCopy device is the same as that of a PLD?
2.	Can Altera provide extraction timing data after HardCopy placement and routing?
3.	Sometimes it is very difficult to have a fully synchronous design. There can be some asynchronous paths, such as in a multi-clock domain design, where a path goes from one clock to another. Can you still guarantee timing in this situation?
4.	What happens if design rules are not followed?
5.	What happens if the customer's system tries to configure the HardCopy device?
6.	Will minimum timing in HardCopy devices be supported (required for I/O issues with tSU and tCO)?
7.	What is the ICCSTANDBY current in a HardCopy device?
8.	Will there be any difference in the I/O timing between the PLD and the HardCopy device?
9.	Will Altera be able to guarantee minimum timing?
10.	Can the SignalTap logic analysis be left instantiated so that a design does not have to be recompiled?
11.	Does the HardCopy device contain the same test circuits as the PLD?
12.	How does the HardCopy clock skew compare to that of the Altera high-density devices?
13.	Are there any additional I/Os in HardCopy devices for testing?
14.	How do you maintain the pin placement to the original PLD?
15.	For a boundary scan, what happens to all the unused I/O pins in a HardCopy device?
16.	Will the customer have to generate board-level test vectors due to the changes in the HardCopy boundary-scan chain ordering?

Business Guidelines (click)

1.	What are the business guidelines for design migration from PLDs to HardCopy devices?
2.	Can additional prototype devices be ordered? If so, what is the unit cost and when must Altera be notified of the request?
3.	Can HardCopy devices be purchased from Altera's authorized distributors?
4.	Do customers pay royalties for ARM-based Excalibur embedded processor HardCopy devices?
5.	What is the license and/or royalty scheme for the MegaCore® and AMPPSM IP functions?
6.	What are the deliverables for design migration from a PLD to a HardCopy device?

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