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Altera introduces the Cyclone™ II FPGA family,
the latest in the Cyclone series of low-cost FPGAs. Altera forever changed
the FPGA industry with the introduction of the Cyclone device family in 2002—
bringing to market the first and only FPGA family designed from the ground up
for the lowest cost. Altera took the same approach and built the Cyclone II family
with each member individually optimized for minimum die size.
The Cyclone II FPGA family offers the same benefits as its
predecessor—a customer-defined feature set, industry-leading performance,
and low power consumption—but with much more density and features—at dramatically
lower costs. Cyclone II devices extend the low-cost FPGA density range up to 68,416
logic elements (LEs) and up to 1.1 Mbits of embedded memory.
Cyclone II devices are manufactured on 300-mm wafers using TSMC¡¯s 90-nm low-k dielectric process,
the same proven process used with Altera¡¯s Stratix¢ç II devices. This process technology will
ensure rapid availability and low cost. By minimizing silicon area, Cyclone II devices can support
complex digital systems on a single chip at a cost that rivals that of ASICs.
All Cyclone II devices are supported by the no-cost Quartus¢ç II Web Edition software.
Quartus II software is the industry¡¯s most advanced design software for FPGAs and provides
a comprehensive suite of synthesis, optimization, and verification tools in a single,
unified design environment. Designers can select from a large portfolio of
intellectual property (IP) cores, and download Altera's unique OpenCore¢ç Plus version of the chosen core(s).
The Quartus II software is used to integrate and evaluate the cores in Cyclone II devices.
Quartus II software's advanced technology reduces development costs and helps bring products to market faster.
Cyclone II Performance & Features
The Cyclone II FPGA series is the right choice for cost-sensitive applications
because it offers the lowest price per LE compared to all other cost-optimized FPGA families.
Each Cyclone II device is designed with an optimal set of features, including:
£ Up to 68,416 LEs for high-density applications
£ Up to 1.1 Mbits of embedded memory for general-purpose storage
£ Up to 150 18x18 embedded multipliers for low-cost digital signal processing (DSP)
applications
£ Dedicated external memory interface circuitry to interface with DDR2, DDR and
SDR SDRAM, and QDRII SRAM memory devices
£ On- and off-chip system timing management using up to 4 embedded PLLs
£ Support for single-ended I/O standards including 64-bit/66-MHz PCI and
64-bit/100-MHz PCI-X (Mode 1) protocols
£ Differential I/O signaling capabilities supporting RSDS, mini-LVDS,
LVPECL, and LVDS for data rates up to 805 megabits per second (Mbps) receiving and
622 Mbps transmitting
£ Automated CRC checking for safety critical applications
£ Fully supports the Nios¢ç II embedded processors
£ Low-cost configuration solution with serial configuration devices
£ No-cost evaluation of IP functions through the Quartus II software's OpenCore Plus
evaluation feature
£ No-cost software support with the Quartus II Web Edition software
Answers to common questions about Cyclone II FPGAs are available on the
Questions & Answers web page. Customer quotes about the new Cyclone II FPGA family are also available.
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