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FPGA performance reaches new heights with the Stratix™ II device family—the industry¡¯s fastest and
highest-density FPGAs. Built on a new and innovative logic structure, Stratix II devices on average deliver 50% faster performance
and offer more than twice the logic capacity of first-generation Stratix FPGAs. Stratix II devices extend the possibilities of
FPGA design, allowing designers to meet the high-performance requirements of today¡¯s advanced systems and avoid developing with
costly ASICs. Based on the award-winning Stratix device family architecture, Stratix II devices are outfitted with a powerful set of
system-level features and incorporate many significant enhancements and new capabilities.
Stratix II FPGAs are manufactured on 300-mm wafers using TSMC¡¯s 90-nm, low-k dielectric process technology. Stratix II devices mark
the debut of an innovative and efficient logic structure that maximizes performance while consuming fewer resources and provides full
backward compatibility with previous-generation architectures. This logic structure increases device densities to never-before-seen
levels, reaching up to 180K equivalent logic elements (LEs) and 9 Mbits of RAM, all at a significantly lower cost than prior-generation
FPGAs.
Stratix II devices were designed in concert with the Quartus¢ç II software to deliver unmatched performance and ease-of-use.
The Quartus II software is the industry¡¯s most advanced development software for high-density FPGAs and provides a comprehensive
suite of synthesis, optimization, and verification tools in a single, unified design environment.
With support for migration to HardCopy™ structured ASICs, Stratix II FPGAs offer the industry's only seamless development path from
FPGA prototype to high-volume, structured ASIC production. Designing with HardCopy devices allows you to reduce development costs and
still get the flexibility and time-to-market advantages associated with FPGAs.
Best-in-Class Features
Stratix II devices improve on the features that set new standards in FPGAs (Figure 1). New device capabilities
such as the new logic structure and design security technology round out the industry¡¯s most advanced FPGA feature set.
New Logic Structure
£ New and innovative logic structure based on adaptive logic modules (ALMs) that packs more
logic into less area and enables faster performance
£ Dedicated arithmetic functionality to efficiently implement adder trees and other
computationally intensive functions
High-Speed I/O Signaling & Interfaces
£ 1-Gbps source-synchronous I/O signaling performance in dedicated serialization/
deserialization (SERDES) circuitry
£ Dynamic phase alignment (DPA) circuitry accelerates maximum performance by dynamically
resolving external board and internal device skew
£ Support for differential I/O signaling levels, including HyperTransport™, LVDS, LVPECL
and differential SSTL and HSTL
External Memory Interfaces
£ Support for the latest external memory interfaces in dedicated circuitry, including
DDR2 SDRAM, RLDRAM II, and QDRII SRAM devices
£ Sufficient bandwidth and I/O pins to support interfacing with multiple, standard 64-bit or
72-bit, 168-/144-pin dual inline memory modules (DIMMs)
Design Security
£ Brings programmable logic functionality and benefits to new applications requiring design
security
£ 128-bit advanced encryption standard (AES) design security using configuration bitstream
encryption technology
£ Key securely stored in FPGA and does not require battery backup or consume logic
resources
TriMatrix™ Memory
£ Up to 9 Mbits of memory in three block sizes: M-RAM, M4K, and M512 blocks
£ Includes parity bits for error checking
£ Performance up to 370 MHz
£ Mixed-width data and mixed-clock modes
Digital Signal Processing (DSP) Blocks
£ More DSP block bandwidth with up to 4X more DSP bandwidth than Stratix devices
£ Dedicated multiplier, pipeline, and accumulate circuitry
£ New rounding and saturation support in Q1.15 format in each DSP block
£ Maximized performance of up to 370 MHz
Clock Management Circuitry
£ Up to 12 on-chip phase-locked loops (PLLs) for device and board clock management
£ Dynamic PLL reconfiguration allowing on-the-fly PLL parameter changes
£ Redundant clock switchover for error recovery and multi-clock systems
On-Chip Termination
£ On-chip, differential and series termination reducing board design complexity and cost
Remote System Upgrades
£ Remote system upgrades for reliable and safe deployment of in-system upgrades and bug
fixes
£ Dedicated watchdog circuitry ensures proper functionality after update
Figure 1. Stratix II Device Floorplan
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